LibGuides: CISC 3310 Principles of Computer Architecture (Briskman): Topic 5: Computer Instructions

Materials for Topic 5: Computer Instructions

2. Instruction Set Architecture (e-book chapter)
Citation: Parthasarathi, Ranjani. "2. Instruction Set Architecture." Computer Architecture. INFLIBNET Centre, 24 July 2018, https://www.cs.umd.edu/~meesh/411/CA-online/index.html, Accessed 30 June 2024. License: CC BY-NC: Attribution-NonCommercial.
URL: https://www.cs.umd.edu/~meesh/411/CA-online/chapter/instruction-set-architecture/index.html
8. Execution of a Complete Instruction – Datapath Implementation (e-book chapter)
Citation: Parthasarathi, Ranjani. "8. Execution of a Complete Instruction – Datapath Implementation." Computer Architecture. INFLIBNET Centre, 24 July 2018, https://www.cs.umd.edu/~meesh/411/CA-online/index.html, Accessed 30 June 2024. License: CC BY-NC: Attribution-NonCommercial.
URL: https://www.cs.umd.edu/~meesh/411/CA-online/chapter/execution-of-a-complete-instruction-datapath-implementation/index.html
9. Execution of a Complete Instruction – Control Flow (e-book chapter)
Citation: Parthasarathi, Ranjani. "9. Execution of a Complete Instruction – Control Flow." Computer Architecture. INFLIBNET Centre, 24 July 2018, https://www.cs.umd.edu/~meesh/411/CA-online/index.html, Accessed 30 June 2024. License: CC BY-NC: Attribution-NonCommercial.
URL: https://www.cs.umd.edu/~meesh/411/CA-online/chapter/execution-of-a-complete-instruction-control-flow/index.html
10. Pipelining – MIPS Implementation (e-book chapter)
Citation: Parthasarathi, Ranjani. "10. Pipelining – MIPS Implementation." Computer Architecture. INFLIBNET Centre, 24 July 2018, https://www.cs.umd.edu/~meesh/411/CA-online/index.html, Accessed 30 June 2024. License: CC BY-NC: Attribution-NonCommercial.
URL: https://www.cs.umd.edu/~meesh/411/CA-online/chapter/pipelining-mips-implementation/index.html
11. Pipeline Hazards (e-book chapter)
Citation: Parthasarathi, Ranjani. "11. Pipeline Hazards." Computer Architecture. INFLIBNET Centre, 24 July 2018, https://www.cs.umd.edu/~meesh/411/CA-online/index.html, Accessed 30 June 2024. License: CC BY-NC: Attribution-NonCommercial.
URL: https://www.cs.umd.edu/~meesh/411/CA-online/chapter/pipeline-hazards/index.html
12. Handling Data Hazards (e-book chapter)
Citation: Parthasarathi, Ranjani. "12. Handling Data Hazards." Computer Architecture. INFLIBNET Centre, 24 July 2018, https://www.cs.umd.edu/~meesh/411/CA-online/index.html, Accessed 30 June 2024. License: CC BY-NC: Attribution-NonCommercial.
URL: https://www.cs.umd.edu/~meesh/411/CA-online/chapter/handling-data-hazards/index.html
13. Handling Control Hazards (e-book chapter)
Citation: Parthasarathi, Ranjani. "13. Handling Control Hazards." Computer Architecture. INFLIBNET Centre, 24 July 2018, https://www.cs.umd.edu/~meesh/411/CA-online/index.html, Accessed 30 June 2024. License: CC BY-NC: Attribution-NonCommercial.
URL: https://www.cs.umd.edu/~meesh/411/CA-online/chapter/handling-control-hazards/index.html
14. Dynamic Branch Prediction (e-book chapter)
Citation: Parthasarathi, Ranjani. "14. Dynamic Branch Prediction." Computer Architecture. INFLIBNET Centre, 24 July 2018, https://www.cs.umd.edu/~meesh/411/CA-online/index.html, Accessed 30 June 2024. License: CC BY-NC: Attribution-NonCommercial.
URL: https://www.cs.umd.edu/~meesh/411/CA-online/chapter/dynamic-branch-prediction/index.html
15. Exception handling and floating point pipelines (e-book chapter)
Citation: Parthasarathi, Ranjani. "15. Exception handling and floating point pipelines." Computer Architecture. INFLIBNET Centre, 24 July 2018, https://www.cs.umd.edu/~meesh/411/CA-online/index.html, Accessed 30 June 2024. License: CC BY-NC: Attribution-NonCommercial.
URL: https://www.cs.umd.edu/~meesh/411/CA-online/chapter/exception-handling-and-floating-point-pipelines/index.html
16. Advanced Concepts of ILP – Dynamic Scheduling (e-book chapter)
Citation: Parthasarathi, Ranjani. "16. Advanced Concepts of ILP – Dynamic Scheduling." Computer Architecture. INFLIBNET Centre, 24 July 2018, https://www.cs.umd.edu/~meesh/411/CA-online/index.html, Accessed 30 June 2024. License: CC BY-NC: Attribution-NonCommercial.
URL: https://www.cs.umd.edu/~meesh/411/CA-online/chapter/advanced-concepts-of-ilp-dynamic-scheduling/index.html
17. Dynamic scheduling – Example (e-book chapter)
Citation: Parthasarathi, Ranjani. "17. Dynamic scheduling – Example." Computer Architecture. INFLIBNET Centre, 24 July 2018, https://www.cs.umd.edu/~meesh/411/CA-online/index.html, Accessed 30 June 2024. License: CC BY-NC: Attribution-NonCommercial.
URL: https://www.cs.umd.edu/~meesh/411/CA-online/chapter/dynamic-scheduling-example/index.html
18. Dynamic scheduling – Loop Based Example (e-book chapter)
Citation: Parthasarathi, Ranjani. "18. Dynamic scheduling – Loop Based Example." Computer Architecture. INFLIBNET Centre, 24 July 2018, https://www.cs.umd.edu/~meesh/411/CA-online/index.html, Accessed 30 June 2024. License: CC BY-NC: Attribution-NonCommercial.
URL: https://www.cs.umd.edu/~meesh/411/CA-online/chapter/dynamic-scheduling-loop-based-example/index.html
19. Dynamic scheduling with Speculation (e-book chapter)
Citation: Parthasarathi, Ranjani. "19. Dynamic scheduling with Speculation." Computer Architecture. INFLIBNET Centre, 24 July 2018, https://www.cs.umd.edu/~meesh/411/CA-online/index.html, Accessed 30 June 2024. License: CC BY-NC: Attribution-NonCommercial.
URL: https://www.cs.umd.edu/~meesh/411/CA-online/chapter/dynamic-scheduling-with-speculation/index.html
20. Exploiting ILP with Software Approaches 1 (e-book chapter)
Citation: Parthasarathi, Ranjani. "20. Exploiting ILP with Software Approaches 1." Computer Architecture. INFLIBNET Centre, 24 July 2018, https://www.cs.umd.edu/~meesh/411/CA-online/index.html, Accessed 30 June 2024. License: CC BY-NC: Attribution-NonCommercial.
URL: https://www.cs.umd.edu/~meesh/411/CA-online/chapter/exploiting-ilp-with-software-approaches-i/index.html
Unit 2: Instructions: Hardware Language (online course unit)
Citation: “CS301: Computer Architecture | Unit 2: Instructions: Hardware Language.” Saylor Academy, 2010, learn.saylor.org/course/CS301. Accessed 30 June 2024. License: CC BY: Attribution.
URL: https://learn.saylor.org/course/view.php?id=71§ionid=15502
Unit 5: Designing a Processor (online course unit)
Citation: “CS301: Computer Architecture | Unit 5: Designing a Processor.” Saylor Academy, 2010, learn.saylor.org/course/CS301. Accessed 30 June 2024. License: CC BY: Attribution.
URL: https://learn.saylor.org/course/view.php?id=71§ionid=15528
Chapter 3, Section 1: The CPU (pdf book section)
Citation: Wienand, Ian. (2019). "Chapter 3, Section 1: The CPU." Computer Science from the Bottom Up, https://www.bottomupcs.com/. License: CC BY-SA: Attribution-ShareAlike.
URL: https://www.bottomupcs.com/csbu.pdf#page=64
Chapter 6, Section 5: An Arithmetic and Logic Unit - ALU (pdf book section)
Citation: Bergmann, Seth D. (2018). "Chapter 6, Section 5: An Arithmetic and Logic Unit - ALU." Computer Organization with MIPS, https://rdw.rowan.edu/oer/9/. License: CC BY-NC-ND: Attribution-NonCommercial-NoDerivs.
URL: https://rdw.rowan.edu/cgi/viewcontent.cgi?article=1008&context=oer#section.6.5
Chapter 6, Section 6: Construction of the ALU (pdf book section)
Citation: Bergmann, Seth D. (2018). "Chapter 6, Section 6: Construction of the ALU." Computer Organization with MIPS, https://rdw.rowan.edu/oer/9/. License: CC BY-NC-ND: Attribution-NonCommercial-NoDerivs.
URL: https://rdw.rowan.edu/cgi/viewcontent.cgi?article=1008&context=oer#section.6.6
Chapter 7: MIPS Datapath (pdf book chapter)
Citation: Bergmann, Seth D. (2018). "Chapter 7: MIPS Datapath." Computer Organization with MIPS, https://rdw.rowan.edu/oer/9/. License: CC BY-NC-ND: Attribution-NonCommercial-NoDerivs.
URL: https://rdw.rowan.edu/cgi/viewcontent.cgi?article=1008&context=oer#chapter.7
Appendix: MIPS Instruction Set (pdf book chapter)
Citation: Bergmann, Seth D. (2018). "Appendix: MIPS Instruction Set." Computer Organization with MIPS, https://rdw.rowan.edu/oer/9/. License: CC BY-NC-ND: Attribution-NonCommercial-NoDerivs.
URL: https://rdw.rowan.edu/cgi/viewcontent.cgi?article=1008&context=oer#page=373
Chapter 9, Section 1: Instruction Set Architectures (pdf book section)
Citation: Bergmann, Seth D. (2018). "Chapter 9, Section 1: Instruction Set Architectures." Computer Organization with MIPS, https://rdw.rowan.edu/oer/9/. License: CC BY-NC-ND: Attribution-NonCommercial-NoDerivs.
URL: https://rdw.rowan.edu/cgi/viewcontent.cgi?article=1008&context=oer#section.9.1
Chapter 9, Section 2: Addressing Modes (pdf book section)
Citation: Bergmann, Seth D. (2018). "Chapter 9, Section 2: Addressing Modes." Computer Organization with MIPS, https://rdw.rowan.edu/oer/9/. License: CC BY-NC-ND: Attribution-NonCommercial-NoDerivs.
URL: https://rdw.rowan.edu/cgi/viewcontent.cgi?article=1008&context=oer#section.9.2
Chapter 3: The Processor (pdf book chapter)
Citation: Viswanath, Divakar. "Chapter 3: The Processor." Scientific Programming and Computer Architecture. The MIT Press, 2017, https://mitpress.mit.edu/9780262036290/scientific-programming-and-computer-architecture/. License: CC BY-NC-ND: Attribution-NonCommercial-NoDerivs.
URL: https://library.oapen.org/bitstream/handle/20.500.12657/26041/Scientific%20Programming%20and%20Computer%20Architecture.pdf#page=84

Videos on Topic 5: Computer Instructions

"How a CPU Works" by "In One Lesson"

YouTube URL: https://www.youtube.com/watch?v=cNN_tTXABUA

Citation: "How a CPU Works." YouTube, In One Lesson, 15 Mar. 2013. License: CC BY: Attribution.

URL: www.youtube.com/watch?v=cNN_tTXABUA

"Endianness Explained" by Aaron Yoo

YouTube URL: https://www.youtube.com/watch?v=LxvFb63OOs8

Citation: Yoo, Aaron. "Endianness Explained." YouTube, 29 Jul. 2019.
URL: www.youtube.com/watch?v=LxvFb63OOs8

"The Fetch-Execute Cycle: What's Your Computer Actually Doing?" by Tom Scott

YouTube URL: https://www.youtube.com/watch?v=Z5JC9Ve1sfI

Citation: Scott, Tom. "The Fetch-Execute Cycle: What's Your Computer Actually Doing?" YouTube, 29 Jul. 2019.
URL: www.youtube.com/watch?v=Z5JC9Ve1sfI

"Processor Addressing Modes" by Computer Science

YouTube URL: https://www.youtube.com/watch?v=TGcjn8zMhfM

Citation: "Processor Addressing Modes." YouTube, Computer Science, 27 Nov. 2018.
URL: www.youtube.com/watch?v=TGcjn8zMhfM

"Course 1 Fundamentals of Computer Architecture", a Playlist by Prof. Dr. Ben H. Juurlink

This video belongs to playlist called "Course 1 Fundamentals of Computer Architecture" at https://www.youtube.com/playlist?list=PLeWkeA7esB-MuCn8XQWAarM7zvimE0yme. In this playlist, videos 18 to 27 are the most relevant to our topic; the current video is #18.

YouTube URL: https://www.youtube.com/watch?v=zPmfprtdzCE

Citation: Juurlink, Ben H. "1 3 1 Pipelining Principles." YouTube, 22 Oct. 2018.
URL: https://www.youtube.com/watch?v=zPmfprtdzCE

"Hardwired vs microprogrammed control" by Abelardo Pardo

YouTube URL: https://www.youtube.com/watch?v=pI7mDvUwiWE

Citation: Pardo, Abelardo. "Hardwired vs microprogrammed control." YouTube, 7 Sep. 2013. License: CC BY: Attribution.

URL: www.youtube.com/watch?v=pI7mDvUwiWE

"An intuitive approach for understanding the CPU and RAM" by "In One Lesson"

YouTube URL: https://www.youtube.com/watch?v=-IyB8hBkA9w

Citation: "An intuitive approach for understanding the CPU and RAM." YouTube, In One Lesson, 24 Feb. 2023. License: CC BY: Attribution.

URL: www.youtube.com/watch?v=-IyB8hBkA9w

CPU Visual Simulator

Citation: Cancelli, Jonathan et al. "CPU Visual Simulator (CPUVSIM)". GitHub, 2021.
URL: https://cpuvisualsimulator.github.io/

Usage: To watch the simulator in action, click "Examples" on the top-right menu, choose one of the given examples, and then press the Play button (►) under "Program" at the middle-bottom of the screen. The simulator will start running the underlying program and show how each of the instructions of that program travels through the CPU and its buses, resulting in the correct answer at the end. Alternatively, press the Play button (►) under "Micro step", instead, to see the execution of just one instruction at a time.

For more information about what each example program does, and to learn what each of the computer instructions inside RAM (Random Access Memory = computer's memory) means, please view the manual page of the guide: see the box below.

CPU Visual Simulator: Manual

Citation: Cancelli, Jonathan et al. "CPU Visual Simulator: Manual". GitHub, 2021.
URL: https://cpuvisualsimulator.github.io/manual